FTD Automation Pvt. Ltd.

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Data Sheet

Pre- and post-route signal integrity analysis

CadenceĀ® OrCADĀ® Signal Explorer provides a scalable, cost-effective pre- and post-layout system interconnect design and analysis environment. Signal Explorer is tightly integrated with Cadence OrCAD PCB Editor and is a component of the Cadence OrCAD PCB Designer suites. As your level of signal integrity challenges and sophistication grows, Signal Explorer provides an easy upgrade path to the advanced Cadence Allegro PCB SI technologies.

Signal Explorer addresses the challenges created as a result of increasing design density, complexity, and faster edge rates by enabling designers to address signal integrity (SI) issues throughout the design process. This approach allows design teams to eliminate time-consuming simulate-fix-simulate iterations at the back-end of a design process.

Signal Explorer allows users to weigh the trade-offs involved in routing choices (rules) that affect cost relative to electrical performance and reliability. Once developed, these optimum constraints then drive the physical layout and routing of the PCB.


  • Provides cost-effective, scalable, pre- and post-layout system interconnect design and analysis
  • Improves circuit performance
  • Increases circuit reliability
  • Eliminates the need to translate designs databases to run simulations
  • Saves time via a virtual prototyping environment that is seamlessly integrated with OrCAD PCB Editor

Feature Summary

Macro modeling support (DML) Graphical topology editor
IBIS 5 support Lossy transmission lines
IBIS ICM model support Coupled (3 net) simulation
Spectre-to-DML conversion Differential pair exploration and simulation
HSPICE-to-IBIS conversion

New Capabilities in Release 16.6

  1. HSPICE interface
  2. Differential signal constraint capture
  3. Comprehensive simulation
  4. Sweep simulations
  5. Constraint development and capture of topologies
  6. Wide-band analytical via model generator

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