Allegro FPGA System Planner

Allegro FPGA System Planner

Create an optimum correct-by-construction pin assignment for FPGA-PCB co-design

The Cadence^® Allegro^® FPGA System Planner offers a complete, scalable technology for FPGA/PCB co-design that allows users to create an ideal correct-by-construction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectivity, FPGA device pin assignment rules, and placement of FPGAs on the PCB. With automatic pin-assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB. This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches while shortening the design cycle time.

Key Benefits:

• Accelerates integration of FPGAs with Cadence PCB design creation environments
• Eliminates unnecessary, frustrating design iterations during the PCB layout process
• Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors
• Reduces PCB layer count through placement-aware pin assignment and optimization
• Enables interface-based connectivity definition for the FPGA system
• Enables placement-aware pin assignment synthesis that is FPGA-DRC accurate
• Allows architectural exploration for FPGA system
• Speeds ASIC prototyping using FPGAs

Screenshot: Allegro FPGA System Planner

Datasheets: Allegro FPGA System Planner.pdf