Allegro Sigrity PI Base

Allegro Sigrity PI Base

Allegro Sigrity PI Base

Power Integrity analysis for both the non-expert and the expert

 

The Cadence® Allegro® Sigrity™ PI Base is an interactive design and analysis environment with Allegro DRC markers locating areas that need layout changes to improve power integrity (PI). In addition, advanced modeling and PI simulation is provided in support of Power Delivery Network (PDN) analysis of high-speed and/or high-current designs. The Allegro Sigrity PI Base simulates PDNs at the package or board level.

Users of the Allegro Sigrity PI Base technology can perform DC analysis using the Sigrity PowerDC engine without having to perform any manual data translation. Set-up is automated so that the default analysis settings are always in place for the user. The integrated solution for layout and analysis can be used throughout the design process. User-friendly guidance is offered to assist the layout team on how best to optimize the PDN.

Also included with the Allegro Sigrity PI Base is a power feasibility editor (PFE) to aid in decoupling capacitor selection and placement. The Allegro constraint manager is enabled with Power Integrity Constraint Sets (PICsets) that can be reused from design to design. When used during the component placement phase of PCB or IC package design, the PICset shows the layout designer where to place the decoupling capacitors so they will be most effective.

Key Benefits:
  • Locates areas needing layout changes to improve power integrity
  • Provides advanced modeling and PI simulation for PDN analysis
  • Simulates PDNs at package or board level
  • PFE aids in decoupling capacitor selection and placement

 

 

 

Screenshot: Allegro_Sigrity PI Base

Datasheets: Allegro Sigrity PI Base.pdf